Keynote Information at PDP 2019


    Notification extended
    November 27, 2018
    November 30, 2018

    July 21, 2018:
    List of accepted special sessions

    July 21, 2018:
    Call for paper available


Prof. David Atienza (Embedded Systems Lab., EPFL)   


Brain-Inspired Many-Core Servers in the IoT Era



The continuous evolution of manufacturing technologies are enabling the development of more powerful and compact high-performance computing (HPC) servers made of many-core processing architectures. However, this soaring demand for computing power in the new Internet of Things (IoT) era has grown faster than semiconductor technology evolution can sustain, and is producing as collateral undesirable effect a surge in power consumption and heat density in these new HPC servers, which result on significant performance degradation.

In this keynote, I advocate to completely revise the current HPC server architectures. In particular, inspired by the mammalian brain, I propose to design a disruptive three-dimensional (3D) computing server architecture that overcomes the prevailing worst-case power and cooling provisioning paradigm for servers. This new 3D server design champions a new system-level thermal modeling, which can be used by novel proactive energy controllers for detailed heat and energy management in many-core HPC servers, thanks to micro-scale liquid cooling. Then, I will show the impact of new near-threshold computing architectures on server design, and how we can integrate new on-chip microfluidic fuel cell networks to enable energy-scalability in future generations of many-core HPC servers targeting Exascale computing in the IoT era.

Short biography:

David Atienza is Associate Professor of Electrical and Computer Engineering and leads the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in Computer Science and Engineering from UCM (Spain) and IMEC (Belgium). His research interests focus on system-level design methodologies for energy-efficient multi-processor system-on-chip architectures (MPSoC) and next-generation smart embedded systems (particularly wearables) for the Internet of Things (IoT) era. In these fields, he is co-author of more than 250 publications, nine patents, and received several best paper awards in top conferences. He also was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. Dr. Atienza has received the DAC Under-40 Innovators Award in 2018, IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He is an IEEE Fellow and an ACM Distinguished Member.




Prof. Massimo Torquati (University of Pisa)   


Designing a RISC set of parallel building-blocks for parallelism exploitation on multi-cores



Abstracting parallel programming by employing parallel design patterns has received renovated attention in the last decade. The key benefits of parallel patterns are that they abstract over many low-level implementation details thus allowing to decrease the time-to-solution. The definition of suitable and performant parallel abstractions with their associated functional and parallel semantics requires efficient parallel Run-Time Systems (RTSs) capable of delivering adequate performance, possibly close to a hand-tuned parallel solution. One of the challenges is to define efficient and flexible mechanisms and also a clear methodology for designing new parallel abstractions.

In the presentation, we discuss a RISC-like set of parallel building-blocks that can be used to build efficient parallel patterns targeting both data-intensive and also computing-intensive applications for multi-core systems. We focus on stream parallelism showing how the composability and refactorability properties of the building-blocks allow to express and optimize complex computations.

We present the FastFlow implementation of such building-blocks and how they were used to design both high-level parallel patterns as well as to provide support for some performance-oriented DSLs.

Short biography:

Massimo Torquati is an Assistant Professor in Computer Science at the University of Pisa. Before starting to work as an academic researcher in 2010, he worked for several years in the industry having the opportunity to participate in large-scale projects also related to parallel computing. He has published about 100 peer-reviewed papers in conference proceedings, international journals, and books mostly in the fields of parallel and distributed programming and run-time systems for heterogeneous parallel computing platforms. He has been involved in several Italian, EU, and industry-supported research projects including the Artemis SMECY project, the EU H2020 RePhrase, the FP7 STReP RePaRa and ParaPhrase projects. He designed and currently maintains the FastFlow parallel programming library.




Prof. William Fornaciari (University of Milan)   


Dr. Davide Zoni (University of Milan)   


Opportunities and challenges to design an open-hardware SoC in the IoT era



The Internet of Things (IoT) is shaping a tightly interconnected world made of millions of smart objects that are constantly collecting, processing and sharing different data streams. Such devices are usually implemented in the form of embedded general purpose processors that can be eventually coupled with ad-hoc hardware accelerators to deal with the most demanding computational tasks. We note that the IoT applications were confined to the low-bandwidth, bio-inspired domain until few years ago due to the limited computational capacity of the smart objects. In fact, the IoT scenarios are constantly evolving by continuously shaping novel and more demanding applications, i.e., high definition image processing, machine learning and artificial intelligence tasks. Real-time applications represent an additional IoT domain that requires novel and sophisticated low-power platforms. Last, the large number of interconnected objects introduce a wide range of security risks fueled by i) the process and transmission of private information and ii) the possibility for an attacker to physically seize the computing objects. In particular, the Side Channel Attacks (SCAs) represents a new and important security threat since, by leveraging the connection between the processed data and one or more environmental device parameters, i.e., power consumption, they can even breach into a mathematically secure cryptographic primitive.

The keynote is organized in two parts.

First, it overviews the main application domains introduced by the IoT revolution from a microarchitectural-centric perspective. The vision is on a new design methodology to address security, real-time and computational requirements still ensuring low-power and area effective platforms.

Second, a detailed discussion on each of the identified IoT requirements, i.e., security, real-time and computational, is offered considering a new microarchitectural design perspective. We introduce a new open-hardware SoC and RISC-V-based CPU. The proposed platform represents a new design model for the microarchitectural explorations in the IoT domain. The SoC has been developed using SystemVerilog 2012 and it has been implemented on a tiny commercial Xilinx Artix35t FPGA-based platforms due to the renewed interest for this technology demonstrated by both the research community and companies. Note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks, so that the topic, despite the energy efficiency, is really hot!

Short biography:

William Fornaciari, Ms, PhD, is Associate Professor at Politecnico di Milano - DEIB. He published 7 books and over 200 papers, collecting 5 best paper awards, one certification of appreciation from IEEE and holds 3 patents on low power solutions. He has been involved in 18 EU- funded projects. During FP7 he won the 2016 HiPEAC Technology Transfer Award for the output of the FP7 CONTREX project, he served as Project Technical Manager of 2PARMA (ranked as success story by the EU) and he coordinated the HARPA project where he filed a PCT patent on thermal management. In H2020 he is the coordinator of the FET-HPC RECIPE project and principal investigator for POLIMI of the M2DC, SafeCOP and MANGO projects. He cooperated for 20 years with the Technology Transfer Centre of POLIMI, actively working with international companies to the development of leading edge products. He created two startups (IBT Solutions and IBT Systems) in 2013 and 2016, respectively. His research interests cover multi-many cores, NoC, low power design, run time resource management, wireless sensor networks, embedded systems, and thermal management. You can follow me on ResearchGate for more information.

Davide Zoni is a Post-doc Researcher at Politecnico di Milano, Italy. He published more than 30 papers in journals and conference proceedings. His research interests include RTL design and optimization for multi-cores with particular emphasis on low power methodologies and hardware-level countermeasures to side-channel attacks. He received two HiPEAC collaboration grants in 2013 and 2014 and two HiPEAC industrial grants in 2015 and 2017. He also participated in 4 European Projects (2PARMA (2010-2012), HARPA (2013-2016), MANGO (2015-2018) and RECIPE (2018-2021), contributing from the beginning to define the structure and the objectives of MANGO and RECIPE. During his research, he has created a wide network of collaborations beyond the EU projects with universities (UPV, UCY and UNINA) and companies (IMEC and ARM).