On-chip Parallel and Network-based Systems

On-chip parallel and network-based system design to achieve functionality with low energy and high performance requires larger device count SoC design, methodology, architectures and evaluation schemes. Such systems, which are emerging as the architecture of choice for future high performance processors, also require high performance interconnects which are necessary to satisfy the data supply needs of all cores. This session is dedicated to research on on-chip communication technology, architecture, design methods and applications, bringing together scientists and engineers working on on-chip innovations from related research communities, including parallel computer architecture, networking, and embedded systems. Original papers describing new and previously unpublished results are solicited on all aspects of on-chip parallel and network-based systems.

Important Dates:

Paper submission:   10th Sep 2018 5th Oct 2018 15th Oct 2018 30th Oct 2018
Acceptance notification:   17th Oct 2018 15th Nov 2018 23rd Nov 2018 27th Nov 201830th Nov 2018
Camera ready due:   12th Nov 2018 15th Dec 2018 19th Dec 2018
Conference: 13th - 15th Feb 2019


    Notification extended
    November 27, 2018
    November 30, 2018

    July 21, 2018:
    List of accepted special sessions

    July 21, 2018:
    Call for paper available


  • On-chip network architecture (topology, routing, arbitration, ...)
  • Network design for 3D stacked logic and memory
  • Processor allocation and scheduling in CMPs
  • Mapping of applications onto NoCs
  • NoC reliability issues
  • OS and compiler support for NoCs
  • Performance and power issues in NoCs
  • Metrics, benchmarks, and trace analysis for NoCs
  • Multi-core and many-core workload characterization and evaluation
  • Modelling and simulation of on-chip parallel and networked systems
  • Synthesis, verification, debug and test of SoCs
  • On-chip memory and cache architectures
  • SoC and NoC design methodologies and tools
  • On-chip systems for FPGAs and structured ASICs
  • CMP/MPSoCs
  • Floorplan-aware NoC architecture optimization
  • Application-specific SoC and NoC design
  • On-chip networked SoC case studies
  • On-chip parallel programming models and tools
  • Reconfigurable SoCs/NoCs
  • Early reports on system prototypes details
  • On-chip massive SIMD computing
  • I/O interconnects and support for SoCs

Programme Co-chairs:

Nader Bagherzadeh, UC, Irvine, USA

Masoud Daneshtalab, KTH Royal Institute of Technology, Sweden

Masoumeh Ebrahimi, University of Turku and KTH University, Finland and Sweden

Hamid Sarbazi-Azad, Sharif University of Technology, Iran

Programme Committee:

Hossein Asadi, Sharif Univ of Tech, Iran

Mohamed Bakhouya, University of Technology of Belfort Montbeliard, France

Julien Bourgeois, UFC/FEMTO-ST UMR CNRS 6174, France

Diana Goehringer, Ruhr-University Bochum (RUB), Germany

Somayyeh Koohi, Sharif University of Technology, Iran

Seung Eun Lee, Seoul National University of Science and Technology, Korea

Samia Loucif, AlHosn University, United Arab Emirates

Mehdi Modarressi, University of Tehran, Iran

Siamak Mohammadi, School of ECE, College of Engineering, University of Tehran, Iran

Martin Radetzki, University of Stuttgart, Germany

Fredy Rivera, Universidad de Antioquia, Colombia

Nozar Tabrizi, Kettering University, USA

Hamid Zarandi, Amirkabir University of Technology, Iran

Farshad Khunjush, Shiraz University, Iran

Piotr Dziurzanski, University of Staffordshire, UK

Farshad Safaei, Shahid Beheshti University G.C., Iran